Talking About The Full-Mask In The Quantitative Stage Of The Wafer And Chip

existintegrated circuitIn the process,Full-MASK is a key concept that involves the use of models in the process of semiconductor manufacturing.Covering the template is an optical tool for the pattern of the surface of the silicon wafer in the semiconductor optical process.There are tiny patterns on the mask, which will be transferred to the lithographs of the silicon wafer through the optical carvings, thereby defining the function area and wiring layer of the chip.

1. The basic role of covering a model

Covering the template is a tool for creating a specific pattern on the wafer.During the semiconductor manufacturing process, photocalism is one of the key process steps. The patterns on the cover -up model are transferred to the lithography glue through steps such as exposure, display and other steps.The pattern of the mask usually represents one or more device layers, such as grids, contact holes, and metal interconnection.

2. Classification of Covering Model

In the manufacturing of integrated circuits, the mask can be divided into two main types:

FULL-MASK: The cover template covering the entire wafer is usually used for the exposure of the full chip.The pattern of this cover -up model will accurately cover the entire exposure area of the wafer, which is suitable for large -scale production.

RETICLE: Compared with Full-Mask, RETICLE usually covers part of the wafer. After each exposure, the step scanner of the mobile optical exposure system needs to be repeated to cover the entire wafer.

3. detailed definition of full-mask

Full-MASK refers to a complete cover-up, which is one-time covered and exposed during the exposure.The advantage of this mask is:

High efficiency: The pattern transfer of one or more chip areas can be completed at one time in production. No need to be exposed multiple times, suitable for mass production。

High accuracy: reducing the confrontation error in repeated exposure, and improved the accuracy and consistency of the pattern.

High cost: Because of its wide coverage and complicated patterns, productionThe cost of Full-Mask is high. Once the design is changed, you need to re-make a cover-up.

4. Chip design process

In the chip design process,Full-Mask usually refers to using a complete mask set in the process of lithography.This mask contains the mask required for all levels of chip manufacturing. It is a complete set for full chip manufacturing.The chip design process roughly includes three main stages: front -end design, back -end design, and manufacturing:

Front -end design (Front-End Design: Including design specifications, RTL design, comprehensive, functional verification, etc.These steps are mainly designed to the functionality of the chip.

Back -end design (Back-End Design: Including layout wiring, timing analysis, power consumption optimization, layout design, etc.These steps ensure that the physical implementation of the chip meets the design requirements.

manufacture: Through the process steps such as lithography, etching, and sedimentation, it will be designed on the silicon wafer.

5. The role of Mask Set in chip manufacturing

During the manufacturing process, the mask is the key part of the lithography process.The mask contains the pattern of each layer of the chip design, which are transferred to the silicon wafer through the lithography process.Each layer of patterns defines a certain structure of the chip, such as gate, sources, metal interconnection, etc.

FULL-MASK: Full-Mask refers to a whole set of mask, covering all the levels required in chip manufacturing.For a complete chip manufacturing process, dozens or even hundreds of mask may be required. Each cover template corresponds to a process step (such as different metal layers, contact holes, grid structures, etc.).

effect:Full-MASK is used for full-mass production, which means that all mask is verified and can be used for large-scale production to ensure that the production chips meet the design specifications and quality requirements.

6. The key steps of FULL-MASK in chip production

Design verification: Before generating a mask, you need to comprehensively verify the design, includingDRC (DESIGN Rule Check), LVS (Layout VS Schematic), and DFM (Design For Manufacturing))examine.These verification steps ensure that the design can be manufactured and reaches a high yield.

Modeling: Based on the design files that pass the verification, make a mask of each layer.The production accuracy of the mask directly affects the characteristic size and performance of the final chip.

Light engraving process: Use the cover -up model to transfer the design of the design to the silicon wafer.This process involves multiple steps such as exposure, development, and etching. The control of accuracy and the control error is the key to ensuring chip performance and yield.

Production verification and optimization: useFull-MASK conducts the first batch of trial production to verify the process process and product performance to ensure that all key parameters are within the specification range.If you find a problem, you need to perform process optimization and mask correction (Mask Revision).

Introduction to mass production: Once the trial production verification is approved,Full-Mask enters the mass production phase to ensure that the consistency and performance of chip produced in large quantities meet expectations.

7. FULL-MASK and Reticle Limitations

In advanced nodes, due to the continuous reduction and complexity of the size of the pattern, the cover of the model may be encountered (RETICLE FIELD SIZE Restrictions.To solve this problem, multiple Multi-Patterning technology is usually used, or the design is cut to adapt to the restrictions of the mask.

8. Full-Mask's technical challenge

In the advanced process, as the size of the node shrinks (such as28nm and below), the production of Full-Mask has become more complicated because the resolution and accuracy of the pattern are higher.In this case, FULL-MASK's challenge includes:

Optical resolution limit: coverThe mold component needs to adapt to the resolution limit of the optical carvings, so it is usually necessary to useOPC (optical adjacent correction) and other mask enhancement technology to improve the quality of pattern.

Design rules and complexity: With the reduction of process nodes, the design of mask needs to consider more electrical effects and optical effects, such as scattering and diffraction.

challenge: In a more advanced process (such as7nm and below), the production of mask has become more complicated and expensive.The production time and cost of each layer of mask are very high, and you need to ensure that every detail of the design is perfect.

Solution: By optimizing the process process and improvement of the manufacturing technology of mask (such asEUV lithography), and comprehensive DFM optimization during the design phase, can reduce the challenges related to Full-Mask and improve production efficiency and yield.

With the reduction of nodes and the increase of design complexity,Full-Mask's design and manufacturing facing increasing technical challenges, it needs to rely on advanced photocalism technology and mask enhancement methods to ensure the final pattern quality.Full-MASK is an important optical tool in semiconductor manufacturing, especially in large-scale mass production with high efficiency and accuracy.