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Home > Industry Information > Transplant The ASIC IP Nuclear On The FPGA -Update The Concept And Promote Changes To Complete The Task Full Of Challenges!

Transplant The ASIC IP Nuclear On The FPGA -Update The Concept And Promote Changes To Complete The Task Full Of Challenges!

Auth： Date：2024/8/2 Source：Shanhai Xincheng Visit：29 Related Key Words: Transplant the ASIC IP nuclear on the FPGA -update the concept and promote changes to complete the task full of challenges!
Previous："The Differences And Principles Of Reserve Protectors And Surge Protectors"
Next："Siruipu Released A Car -Level CAN SIC Transceiver TPT1462XQ"

From the perspective of the technical director of the digital chip design project, this series of articles introduced how to combine the product definition of the chip with the design and verification planning.FPGAUseIPNuclear developmentASICWhen the prototype project, some issues must be considered carefully.The pre -customization function of the article is based on the introductionIPThe necessity of the nuclear starts, by explaining developmentASICIt is necessary to consider the prototype designIPNuclear correlation factors, shared the use in detail with eight important topicsASICUsedIPCome inFPGAThe factors that need to be considered when designing the prototype verification system.

 

In the previous article, we introduced itASIC IPTransplantFPGAThe necessity on the prototype platform, and the various considerations in the design of the prototype design generally overview, analyze and developASICThe prototype verification design needs to be consideredIPNuclear -related factors, as well as the first theme of the eight major themes shared by experience, clearly clear the demand and different discoveries.This article isSmartDVDigital chip design experience sharing the second article of a series of articles, will continue to share the second to fourth theme, includingFPGAThe basic concepts, common challenges and basic adjustments of the prototype.

 

As the world's leading verification solution and designIPProvider,SmartDVProduct research and development and engineering application teams have rich design and verification experience.Large capacity in domesticFPGAChip andIPNew products are constantly being available today,SmartDVAnd its wholly -owned subsidiary of China is willing to be with the countryFPGAChip developer,RISC-V IPand otherIPProvider, integrated circuit design center(ICC)Cooperation to jointly develop local digital chip design companies based on local localFPGAInnovative technologies and products such as verification and design platform.

 

theme1: A prototype and finalASICWhat is the difference between the requirements between implementation?

 

theme2: UseFPGAWhat basic concepts do you think of when designing prototypes?

 

theme3: Will be dedicated toASICTechnologyIPNuclear transplantationFPGAWhat difficulties do you usually encounter in architecture?

 

theme4: To supportFPGAThe prototype usually needs to be rightASIC IPWhat changes are made?

 

theme5: How do we ensure itFPGARealize the required performance?

 

theme6: What are the factors that must be considered in the clock?

 

Topic 7: If the target technology isFPGA, NotASICThen how to testIPNuclear function?

 

theme8: What should the design team keep in mind?

 

theme2:In useFPGAWhat basic concepts do you use when designing prototype design?

 

Reusability pairIPNuclear is important: These cores should be used as universal as much as possibleRTLCode description.This is to ensure it forASICThe implementation of the circuit description can also be used in the prototype design environment without the need for major changes.This is very important, because one of the tasks of prototype design is to checkRTLThe correctness of the code.

 

Any deviation in the implementation will bring risks, useASICLogicalRTLCode replacement is specific forFPGAIn examples, functional errors occur.Using the same code library as much as possible, the function that has been verified during the design period of the prototype can be added.ASICThe possibility of retention in implementation.About impossible to always avoid specific inFPGAThe reason for the component is instantiated, we will be on the theme of the next4Merceable more detailed discussion: In order to support the basedFPGAThe prototype usually needs to be rightASIC IPWhat changes do the nuclear do?

 

UseASICPositive verification in the target architectureIPNucleIPThe provider is successfully transplantedFPGAIn components, huge advantages can be provided.This means that not only the workload required for creating circuits can be greatly reduced, but also uses pre -customized circuit components that have been widely used in this field.ASICThe probability of detecting failure after streaming is also greatly reduced.In this case, it is important not only to reuse pureRTLCode, and can also reduce creation logic and layout wiring (P&R) Set the workload of the script and other required constraints, because these are usually withIPProvided together.All of this can be greatly simplifiedIPNuclear integration.

 

Other standards that are conducive to prototype design are:1）FPGAChoice and2)dedicatedEDAUse of tools.In principle, by selecting the capacity as large as possible and fastFPGA, Or use the pre -customized pre -customized based on commercializationFPGAThe prototype design development board can greatly simplify the work of prototype design.

 

 

 

Digilent Genesys 2 FPGADevelopment board is a commonly applicable case of prototype design platform (picture©Digilent）

 

WillIPNuclear integration to a complexASICIn the design, it usually brings itFPGAExpectation of the same function.The distinction must be made between the two use cases: on the one hand, it is used for prototype design scenarios;ASICBefore the chip), the relevant firmware and software were tested.

 

becauseFPGAProgrammable, use in circuit verificationFPGAIt has become an established standard method to detect and eliminate errors in the implementation of circuit implementation through iterative methods.Compared with pure simulation methods,FPGASupport more test cycles, so it can find and eliminate errors that may be difficult to find in pure simulation verification methods.As a result, the verification coverage has increased significantly.Because the verification is either implemented in real time, it is performed at a slightly reduced clock rate, and even long -term testing can be performed.

 

theme3: Will specificallyASICTechnical designIPNuclear transplantationFPGAWhat difficulties do you usually encounter in architecture?

 

Contrary to people's assumptions,IPThe use of nuclear use is usually not a purely insert, that is, not through the use of standardized components to ensure the circuit function that can be used immediately.If the target architecture isFPGAThe result is even more so.on the contrary,IPThe use of nucleus requires accurate planning of various parameters.The very important thing is that many of them should be considered hereIPNuclear is dedicated toASICThe designs, and at first, did not intend to transplant it toFPGAIn architecture.

 

also,IPThe nuclear is usually created to meet the requirements of various circuit implementation.One user may need some characteristics of the kernel, and the other may need different characteristics, settings or constraints.this meansIPDuring the realization of its own realization, the possible application scenarios must be considered, and all possible configurations must be tested.

 

The following criteria need to be considered:

 

existASICThe clock frequency of the circuit implemented on top can usually be compared withFPGAThe clock frequency is higher.Thus, inFPGAIn implementation, only the characteristics of actual needs should be used.In useIPWhen nucleus, if parameterization is used to create relatedRTLCode, and these code can easily meet their own needs, which will bring great help.This can also ensure that the required functions are provided without major delay.

 

In some cases, it is still necessary to reduceFPGAThe system frequency (for example, lower toASICOne -half or tenth of the clock frequency).Especially for the interface classIPIn terms of, this may be a complicated job, which requires additional changes to external and related software and firmware.When creating functions, take preventive measures to reduce the system clock rate. ForIPSuppliers are very important.

 

AlthoughPHYThis simulation circuit can be usedASICOn, but transplant the circuit function toFPGAIn the case, the situation is not the case.In some cases, the simulation interface can be used byFPGA SerDes IO(In all modernFPGAThe device is usually provided) or a high -speed transceiver to implement it, or by creating a digital simulationPHYLet's simulate to eliminate the external externalPHYEquipment needs.However, in order to provide andASICSimulation with the same functionPHYInterface, based onFPGAThe prototype needs to use this external hardware component.The important thing is to ensureIPandPHYThe communication between interfaces can not only talk between different components, but also understand each other.

 

theme4: To supportFPGAThe prototype must usually be rightASIC IPWhat changes are made?

 

As mentioned earlier,IPNuclear should use universalRTLCode description.The creation of general code means that it should be avoided as much as possibleFPGAOut such as storage,IOTreatment of modules, clock buckle and other specific components instantiated.This is possible in some areas, but it is not always realized due to various reasons.There are many reasons for this. One of the examples here is to use memory implementation:

 

Store components.ASICVersionRTLCode may contain fromASICThe unit library selected and used for instantiated memory components.Such examples cannot be directly mapped toFPGAIn the middle, becauseFPGALogic comprehensive tool cannot be understoodASICLibrary file; therefore, components from the unit library are unknown, resulting inFPGABlack box forms in the tool stream.Therefore, it is not possible to map this storage component directly toFPGAStorage structure provided above.Specifically forASICSite and designed dedicatedFPGALogic comprehensive tools can be readASICThe unit library, but the cost of such tools is extremely high and must be purchased separately.ifASIC RTLIncluding instances from a supplier unit library (e.g.TSMC 28), It is necessary to use itFPGAThe storage structure provided above is used to model a storage unit.ASICThe storage unit selected in the unit library has the same function.

Parameterization method.becauseIPNuclear is used in a variety of applications, so I hope to use parameters to describe it.For example, it can control the wholeIPThe storage size of the nuclear is usually meaningful.This makes the size and restrictions of the storage unit according to the user's own needsFPGAThe use of resources will become easier.

The register array.ASICVersionRTLThe code may contain the register array, and these register array realizes memory function in the desired configuration.Such array is usually notFPGALogical comprehensive tool recognition is memory, and it will not be mapped toFPGAIn the memory available, it is implemented by using the register.However, if the register is used to implement rather than a dedicated memory, thenFPGAThe clock frequency that can be implemented may be greatly reduced because memory implementation requires a large number of registers.In the case of describing large memory as the register array, it may not even be able to map them toFPGAOn, because ofFPGAThe number of registers available on it is not enough to achieve.

The required storage unit.ASICThe required storage is specially created by the target application.FPGAThe mapping of one -to -one will lead to a significant increase in the number of logic doors used, which will lead to a reduced clock frequency.Thus, inFPGAUseASICMemory is usually not desirable.One example is used in security and key applications that have special requirements for functional securityASICThis application requires the correctness of the storage content and the errors that may occur due to external effects.

For example, in order to be able to correct the impact of alpha particles and the single particle flip generated by it (SEU), You need to achieve error correction code (ECC) Circuit.On the other hand, inFPGAThe block memory provided in the default has such circuits. If necessary, the circuit can be activated through special logical comprehensive functional attributes.The redundant circuit with additional logic is almost meaningless, and it is also possible that the required clock frequency cannot be reached because the component core occupies too much.

 

 

 

ASICandFPGAThe storage structure is different, and the clock distribution is very different.Use lock ring/Digital lock ring (PLL/DLL) The circuit can simplify this, but the proprietary onesPLL/DLLThe circuit needs to be instantiated from the corresponding library.

 

OwnerFPGAAll containPLL、DLLOr the combination of the two.These circuits support multiple clock operations, such as clock loss, frequency synthesis (e.g., the input clock frequency division or multiplication method) and the duty -occupying ratio programming.The input clock and output clock can be aligned with phase.AlthoughASICThere are corresponding circuits, but there are differences in function.If neededPLL/DLL, Then fromFPGAIn the corresponding library of the manufacturer, it must be used to the case, and it must ensure that the clock distribution scheme adapts to the goalFPGAArchitecture.

Previous："The Differences And Principles Of Reserve Protectors And Surge Protectors"
Next："Siruipu Released A Car -Level CAN SIC Transceiver TPT1462XQ"

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