Home > Industry Information > Use A Hybrid Signal Oscilloscope To Identify And Maintain Time Illegal Regulations
The time relationship between signals is essential for the reliable operation of digital design.For synchronous design, clock signals are particularly important than data signals.Using a hybrid signal oscilloscope, you can easily determine the time relationship between multiple logic input and clock signals.Establish and maintain time trigger to automatically determine the relationship between clock and data time.
The establishment time refers to the time when the data signal is kept stable (high or low) before the valid clock edge occurs.Keeping time refers to the time when the data signal is kept stable (high or low) after the valid clock edge occurs.The component data manual of the synchronous device (such as a trigger) specifies the setting and maintenance time.It is necessary to meet the requirements of setting and maintaining time in order to ensure that the components work correctly and reliably.
The hybrid signal oscilloscope (MSO) is represented by the simulation and numbers that can capture the signal and display them in a time -associated format. It is very suitable for verifying the signal integrity of the digital signal and debugging the digital circuit.This article takes 5 series MSO as an example, the 2, 4, 5 and 6 series MSO operation methods are the same.The MSO2000 and MSO5000 series oscilloscope follow the same principles, but the user interface is different.They are combined with the basic functions of the performance and logical analyzer of a professional -level oscilloscope.3 series MDO, MDO3000 and MDO4000 series mixed domain oscilloscope also provides 16 -channel logic analyzer functions.Here, any function or ability mentioned in MSO is also suitable for MDO products.
MSOset up
Understand digital time resolution (digital sampling rate)
An important MSO collection specification is time resolution for capturing digital signals.The sampling rate is different between different MSO models.When building and maintaining time measurement, it is very important to understand time measurement resolution.
Digital sampling rate and record length
Table 1 lists the establishment and maintenance time specifications of integrated circuits, usually a few nan seconds or shorter.When testing them with digital logic input using MSO, the time resolution of logic input must be considered.
Set the digital threshold
The digital channels of the hybrid signal oscilloscope are regarded as a digital circuit, and the digital signal is regarded as a high logic or low logic.This means that as long as the bells, overlooking and ground bombs do not cause logical conversion, these simulation features are not a problem for MSO.Like logic analyzers, MSO uses the threshold voltage specified by the user to determine whether the signal is high or logical.
MSOThe analog channel can quickly check the logic amplitude of the digital signal.In Figure 1, the amplifier of the oscilloscope automatically measured the digital signal is about 3.6V.For logical series with symmetrical voltage swing, such as CMOS, the threshold is half of the signal amplitude.However, for the logic series with asymmetric voltage swing, such as TTL (crystal-crystal tube logic), it is usually necessary to refer to the component data table and define the threshold as a low level input voltage (TTLVIL = 0.8V) and minimum high of the logic device.The midpoint (TTLV threshold = 1.4V) between the level input voltage (TTLVIH = 2.0V).
Most of the Tyk MSO provides a threshold settings per channel, which is very useful for debugging circuits with a hybrid logic series.Figure 2 shows that the 5 series MSO uses the 8 -channel TLP058 probe to measure multiple logical signals.The TTL signal threshold is set to 1.7V, the 3.3VCMOS signal threshold is set to 1.65V, and the 5VCMOS signal threshold is set to 2.5V, which can reliably collect various logical signals at the same time.
For the 3 series MDO, MSO2000 and MDO3000 series, the threshold is adjusted according to the probe group (a group of 8 channels). Therefore, the TTL signal will be on a probe group, and the LVPECL signal will be on the second probe group.
Interpret color coding digital waveform display
Digital timing waveforms are very similar to simulation waveforms, only high and low logic.In order to simplify the analysis, TektronixMDO/MSO oscilloscope shows the logic low level as blue, and the logic high level is displayed as green. Even if the transition is not visible, the logic value can be seen.The color of the waveform label is also matched with the color coding of the probe, making it easier to see which signal corresponds and which test point, as shown in Figure 3.
Digital timing waveforms can be combined into a bus.A digital signal is defined as the minimum valid position, and other digital signals represent other binary values until the highest effective position.The oscilloscope then decoded the bus to binary or hexadecimal value.
Eliminate the time bias between channels
Each Tektronix MDO or MSO series oscilloscope has compatible logic probes.In order to simplify digital measurement, oscilloscope will compensate the propagation of logic probes.Therefore, there is no need to perform the difference in digital channel probes.
However, in order to better measure the time between simulation and digital waveforms, it is important to eliminate the time bias of simulation to numbers.In the example shown in FIG. 5, in order to align the analog channel to the digital channel, the position of the 2V (50%amplitude) position of the waveform is aligned with the digital signal at the 2V threshold.Manually adjust the difference to align the simulation channel to the digital channel.The correction process needs to be repeatedly carried out on any other simulation channel.
When replacing the analog probe, check the offset of the analog channel; when measured different logic series, check the digital threshold.After configured the threshold and offset, the oscilloscope can be used to verify and debug digital circuits.
Trigger time measurement
The simplest synchronization logic device is a trigger.The logic state of D input only appears on the Q output after the clock rises (after the transmission of D trigger).MSO is an ideal tool for verifying the working state of the trigger and debugging digital circuits.
At first glance, as shown in Figure 7, the trigger seems to work as expected.The data signal has stabilized a few seconds before the clock rising edge, and it has been stabilized for a few seconds after the clock edge.The transmission delay from the clock edge to the output of Q is about 6 nan seconds.
The data signal changed only 300ps before the clock edge, which was far lower than the establishment of time specifications of 15NS -this is a illegal establishment time.Note that the Q output does not change the state as expected.
Note the gray area around the signal transition in Figure 8.MSO displays these areas to indicate the time uncertainties related to digital sampling rates.
A data signal changes about 300PS after the clock edge.This is far lower than the maintenance time specification of 3NS -this is a time to keep time illegal.Note again that the Q output does not change the state as expected.
Capture establishment and maintain time illegal rules
MSOIt has a special trigger mode to automatically capture each establishment and/or maintain time illegal.Establish and maintain time trigger to measure the time relationship between the clock signal and the data signal (or data signals on certain MSOs), and capture the signal when the establishment time or the maintenance time is lower than the specification.This function simplifies the debugging work, and it can also be used for unattended monitoring.
After checking the data table of 74LVCG74 components, the establishment and maintenance of the trigger parameters will be set to 2 nanoseconds and 1 nan second seconds to capture any violations, as shown in Figure 10.MSO will automatically trigger the first input conditions that violate the specified parameter.
In the previous example, the trigger was established to trigger the input of the trigger.Another method is to trigger the signal error of the device output and capture the input signal for analysis.
In the next example, an intermittent error appeared on an old design based on 74LS74 low -power Schartki TTL technology.The minimum output voltage of the high level is 2.4V, so all high level output signals should reach at least the voltage.The design is based on a 20MHz clock (cycle 50ns), so the width of all output pulses should reach at least half of this cycle.
Not only did intermittent failure on the output of the trigger, but some faults also showed a low range.Figure 12Show a narrow pulseThe low -amplitude pulse captured by the trigger, these pulses do not comply with the specifications of the component.
Use these triggerIn any one in the place, you can capture the input and output signals.FIG. 13 shows the measurement time of the use of the cursor, and clearly indicates that the establishment time is illegal (about 6NS, which is far lower than the minimum value of 20ns).The mixed signal oscilloscope combines the basic logical analyzer function and the simulation signal analysis function of the oscilloscope.
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