AI Applications Have Soared In Complex SOC Demand, And The Opportunities And Challenges Of Advanced Packaging Technologies Such As 2.5D/Chiclet

Benefiting from the great development of the AI industry, the global advanced packaging capacity is currently tight.As the applications such as AI and autonomous driving have become higher and higher, there is still huge development space for subsequent global and China's advanced packaging industry.At the 16th Integrated Circuit Sealing and Testing Industry Chain Innovation Development Forum (CIPA 2024) with the theme of building a new ecosystem of advanced packaging and leading the development of path innovation.The technological development, and how advanced packaging empower the cutting -edge issues such as complex SOC design and other industries.

Challenge of Chiclet technology innovation

Chiclet is an important part of advanced packaging. It is usually translated as core grains or small chips. With the advantages of high performance, low power consumption, and high area utilization, Chiplet is considered an effective means to continue Moore's economic benefits.

Dr. Dai Wenliang, the co -founder of the core and semiconductor co -founder & amp; President Dr. Wen Liang pointed out that Chiclet has accelerated the innovation speed of complex SOCs.In the past, the iterative speed of traditional SOCs was 18-24 months.With the help of CHIPLET technology, technology giants and chip giants will be released every 3 months, or every six months, and the speed of innovation has increased significantly.More importantly, Chiclet allows the support of the algorithm to be more efficient and flexible. There is no need to overthrow the back to design the chip. It only needs to replace the computing unit, which significantly enhances the universality of chip innovation to the algorithm.

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Dr. Dai Wenliang, co -founder of core and semiconductor co -founder & amp; President Dr.

Of course, as a revolutionary technology of chip innovation, the development of Chiclet technology also faces some challenges. For example, Chiclet has improved the complexity and time sensitivity in the wafer management;Some challenges; Chiclet's cost in chip manufacturing also needs to be optimized.

In this regard, Dr. Daiwen Liang specifically mentioned the complexity of Chiclet design, involving feasibility, optimization, and realization.He believes that Chiclet's later development mode Chiclet Store can participate in complex SOC innovation.Taking MCU manufacturers as an example, the original MCU did not need to do large -scale complex SOCs, but MCU is an important part of complex SOC. Therefore, relevant manufacturers can make MCUs into Chiclet that meets the connection standards.Therefore, for the development of CHIPLET, ecosystems are very important. EDA, Fabless, IDM, and wafer agency factories must communicate efficiently. This is also the main reason why cores and semiconductors create advanced package platforms.

Further, if you want to use Chiclet efficiently, advanced packaging technology is inseparable.Chiclet allows the chip to decompose into a specific module. According to the packaging medium material and the packaging process, the implementation method of Chiclet mainly includes the following: MCM, 2.5D packaging, and 3D packaging.He Zhidan, the packaging and development manager of Suzhou Tongfu Chaowei Semiconductor Co., Ltd., said that no matter what advanced packaging form, what you want to do is to transfer the Chiplet to the PCB board through a substrate.At present, Chiclet is beautiful, and the packaging size is getting bigger and bigger, so an obvious problem is to warp.

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He Zhidan, packaging and development manager of Suzhou Tongfu Chaowei Semiconductor Co., Ltd.

The traditional patch machine and backwing method are only about 10 microns, and the challenges and impact are not great.In large packaging that accommodates Chiclet, the warning will reach 150-200 microns, so the traditional packaging form is no longer suitable for Chiclet.He Zhidan pointed out that the number of substrate layers of new products currently reaches 20 layers, and it will even reach 26-28 layers, which means that there will be more serious problems with warnings, which brings greater challenges to lead welding.To deal with warning, the glass substrate is a very good way, but the glass substrate is still in the exploration stage.

The second problem brought by large -scale packaging is heat dissipation.While the advanced packaging chip can meet the demand for high performance computing, artificial intelligence, and power density growth, the problem of heat dissipation has become more complicated.Therefore, solving the problem of chip packaging heat dissipation is a vital task.He Zhidan mentioned that today we hear the power consumption of the chip. Many of them are 600W and 800W, and the power consumption is very high.It is a good cooling solution to make the chip thinner and increase the copper layer coverage.But larger and thinner chips will produce more severe warmers, which is more not conducive to welding.A solution to solving the heat dissipation in Tongfu Chaowei Semiconductor is to use large -area and small heat materials on TIM materials.

Advanced package empowerment large computing chip innovation

Empowerment high -performance calculation is the main driving force for the development of advanced packaging technology. On the other hand, advanced packaging is an important means to create large computing chips.Zhang Weijie, the director of Tianxin Interconnect, said that the current computing power is doubled every 12 months. The high energy effect of the computing power is very important. Advanced packaging is required to achieve high integration and high density, and the power supply module is required to be miniaturized.

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Zhang Weijie, Director of Tianxin Connected Products

In terms of advanced packaging, 2.5D/3D packaging is the direction of the follow -up development of the industry. The board -level fan can also improve system performance.Tianxin Connection is currently doing this work. For example, the company provides processing processes, simulation services, packaging simulation and other services in advanced packaging and system integration solutions.Taking a 5nm chip as an example, Zhang Weijie, based on the scheme of Tianxin connection, implements 4 AI to calculate the DIE interconnection on the 5500 × 4800um WAFER, to create a multi-core architecture, which can reduce the number of FAN-OUT signals and reduce the difficulty of the substrate.

Based on Chiclet and advanced packaging technology, an important feature is a heterogeneous integration. Therefore, the power network will become more and more complicated. How to optimize the power supply is also an important part.Zhang Weijie said that from the perspective of the power supply architecture of the data center, from 380V exchange to 220V and DC, and then converted to 48V power supply.At the same time, under the new power supply architecture, 48V will still be converted to 0.8V or 1.2V. To ensure efficiency, the current will be very large, which will have higher requirements for the heat dissipation and universal capabilities of the power module.The Tianxin connection can provide leading power system schemes relying on wafer -level packaging (WLP), system -level packaging (SIP), and board -level fan -out packaging (FOPLP) platforms.For example, in the FOPLP platform, Tianxin connects GAN, control chips and inductors, which not only has higher efficiency and smaller volume, but also can also achieve common heat dissipation.

In terms of high -performance computing chips, the most typical example is GPGPU.At present, GPGPU is still the cornerstone of AI training tasks.According to Verify Market Research, the global GPU market size will reach US $ 246.51 billion in 2028. The main application areas include AI, data centers and smart cars.Li Yuanxiong, a CTO of Wuhu Lidi Zhixing Semiconductor Co., Ltd., specifically analyzed how the trillion crystal -level GPU chip was achieved through advanced packaging technology.

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Wuhu Lide Zhixing Semiconductor Co., Ltd. CTO Li Yuanxiong

Li Yuanxiong pointed out that the implementation of the GPU of the trillion transistor is horizontal expansion and stacking.In terms of stacking, Intel uses 3D packaging technology FOVEROS, which can stack the computing module vertically instead of traditional horizontal methods during the processor manufacturing process.TSMC uses SOIC (system -level integrated single chips), which can make the computing module directly stacked on the chip in the creative key interface.The main indicators of packaging technology are convex point spacing. The smaller the spacing of the convex point, the higher the packaging integration and the greater the difficulty.TSMC's 3D SOIC's convex point distance can reach the minimum of 6um, ranking first in all packaging technology.In order to achieve this stack, it also requires supporting connection technology, such as high -density silicon -pass holes (TSV) used by TSMC, and high -precision nano -level mixed bond (Hybrid Bonding).

In the horizontal expansion, the main means include fan -out wafer -level packaging processes, etc., which requires reconstruction wafers. The challenge is to ensure that the reconstruction wafers achieve a certain accuracy.Lide Zhixing provides a key device that not only improves the accuracy of reconstruction wafers, but also provides automatic optical testing to enhance the reliability of the chip.

Conclusion

Advanced packaging is the focus of the current and future chip industry development, and it is the main means to create a high -performance computing chip.Of course, there are some additional challenges, whether it is Chiclet or 2.5D/3D packaging, such as the warning and heat dissipation of large packaging, power supply such as heterogeneous integration.The industry is still exploring how to achieve advanced packaging in a better way. This also requires manufacturing and packaging giants to play a better guidance. Advanced packaging requires standard leadership.