One Of The Chip Design Of The Five Parts | Sound And Light Magician -Simulation IC

Episode 1: SimulationIC

simulationIC is a circuit responsible for production, amplification and processing various simulation signals. After the engineer enlarge the analog signal by analog circuit, it is recorded, and then it is a continuous signal.Mobile phone signals, broadband signals and digital signals are discrete signals.

If you say numbersIC is like science, so simulation IC is more like a magic.

The use of computers to auxiliary simulation chip design is essentially to solve high -level micro -division questions after another.

The EDA tool is to do this. The value of TA does not need to explain it.

And our theme today is: simulationWhat are the typical business characteristics of IC design, what are the characteristics of EDA tools used, and how do we use computer technology to improve the calculation efficiency of different business scenarios to help simulate chip engineers to complete chip development work to improve overall efficiency.

This article is mainly fromThe EDA tool computing task perspective set off.

In addition to the calculation angle, scheduling/Management/data/collaborative/cad and other perspectives, that is, another (price) chapter ~

Let me give you a full -process analysis diagram of the simulation chip design:

1. Pre -imitation stage: front -end circuit design and simulation

This stage includes design needs/The description architecture, the input of the schematic diagram, and the previous imitation result comparison design requirements.

The front imitation stage is essentially numerical calculation, so the main frequency requirements are high. Once the resources cannot be met, it will directly causeThe CPU is overloaded, and it can be cut independently between tasks, which is very suitable.Based on the design and simulation of the design drawing, the parameter range is small and the memory requirements are not high.At this stage, most of the multi -Corner and Monte Carlo Monte Carlo tasks have high peak computing power demand and general storage demand.

2. Mid -term: Layout design verification

This stage includes layout design and layout rules inspectionDRC/LVS two steps.

Layout/Verification of the same genus rules, because the calculation does not involve the value of the value, the main frequency requirements are not high, and the demand for heavy memory.The layout can cut the module as a unit, and there are almost countless data between sub -tasks and are suitable for parallel.However

The power demand is higher than before, it is recommended to use multiple cores+Matsered Modern Model, the storage requirements are the highest.

3. Post -imitation phase: back -end simulation

After the imitation includes parasitic parameters extraction, back -end simulation,GDS file formation.

The rear imitation is similar to the front imitation, and multiple tasks can be distributed.However, the post -imitation stage task, because it is possible to involve electromagnetic field simulation, although the essence is calculated, but it needs to meet the high main frequency needs in the case of memory, because the parasitic parameters of various components are added, the computing power requirements are the computing power requirements areThe highest in the three major stages, storage is higher than before, and sometimes it is equivalent to the layout stage.

In the following, we have chosen three typical scenes to start saying:

Two major super -common value calculation scenarios

manyCORNER is also called multi -craftsmanship. Monte Carlo, Monte Carlo, belongs to two different circuit performance and process errors, but it is essentially numerical calculation.deal with.Both the single tasks in these two methods are independent and have no data connection. Both multi -Corner and Monte Carlo are suitable for distributed parallel computing.

Recommended reading: DemystifyMoving table series behind 20,000 VCS tasksThe story of the story explained to how we help users greatly span the stage of large -scale task automation and clustering operations from the stage of single -threading and single -thread operation of single -machine single -threading.It will greatly improve calculation efficiency.

manyCORNER is to arrange the elevation of the element resistance, temperature, voltage and other parameters, and take the pole value (error limit or lower limit of error) of each parameter. Each combination is an independent task.

One combination is oneCorner, all arranges are multiple CORNER.

This is like you come to a two -choice milk tea shop.The sweetness, heat, and how many ingredients of this shop's milk tea shop provides only two options. You either choose not sweet or the sweetest.Every time you drink it, it is all arranged in these options (2*2*2), such as super sugar, hot mouth, and super materials; next time you change a combination of arrangement, sugar -free, multi -ice, no material;Essence

Monte CarloMonte Carlo is arranged and combined endlessly between the upper and lower limit values.

This time you came to a new milk tea shop, the name is endless项 Milk tea shop, the options are completely customized.You can choose any value, for example, the first time you drink 3 points, less ice, without feeding; the next time you feel not sweet enough, not ice, you ordered 6.6 points of sweet, 7.8 points of ice, two pearls with two pearls, add two pearls, add two pearls.Essence

In this way, there will be numerous milk tea with many types of arrangement. This is Monte Carlo.Monte Carlo.

Monte Carlo in countless combinationsMonte Carlo can be used to estimate the scope of the yield, with the combination of value extractionThe more, the more accurate the error estimation range of the process deviation is. The more accurate the predictive range of the actual product yield is, of course, the calculation amount will be doubled.

Regardless of which milk tea shop, this cup of milk tea and that cup of milk tea are independent, you drink you, I drink me.This is how muchCORNER and Monte Carlo Monte Carlo tasks are particularly suitable for the essential reasons for distributed parallel computing.Different tasks, you count you, I calculate me, separate, and more powerful people.

Whether it is an anterior imitation or a rear imitation stage, there is a lot of amountCorner simulation with Monte Carlo with Monte Carlo.Compared with the two, Monte Carlo's Monte Carlo simulation is significantly larger than multiple CORNER because there are many choices and combinations.The front imitation and the back imitation involve more physical parameters. The calculation of the two algorithms will increase geometrically, and the demand for computing power will be greater.On the whole, these two numerical calculation methods and tasks are independent and have great computing power demand. It is one of the typical scenes for us to help users improve efficiency.

Let's find the faults to verify the task

The layout design is to change the design of the design of the circuit schematic into a mask layout containing the actual layout of the wiring plan. The designer draws flowers on the circuit diagram every day.MOS tube, determine how many components and arrangements are used, and how to ensure chip electrical performance, how to make the chip volume the smallest and most money across the layer.

The layout verification is to compare the painted territory and schematic diagrams to ensure that the topology connection between the two is consistent. At the same time, check whether the layout is in line withFoundry's design process.

Layout design and verification, like playing oneEveryone comes to find the game. First of all, several territory designers first painted this picture division of labor together.At the verification stage of the layout, I started to formally play for fault games.The purpose is to check what is wrong with the layout. If you have any problems, hit it back and re -draw.After the painting, continue to check, and the circulation is reciprocating.

If usedLittle F shadow division (layout division) can be divided into 9 shadows, each shadow only needs only needResponsible for finding a nine -thirds of the territory. The more the number of shadows is divided (the number of tasks cutting), the more resources allocated, and the higher the unit efficiency (of course, there is a physical limit of the layout size.To.

More importantly, there is no interference between the cutting territory and the finding of the fault. You change you, I change me.After you have changed the next round, it will not affect me in the last round.There is no need to stop working because of waiting.

The check -up method of cutting and reasonable allocation of resources can make the territory designer not to wait for a computer to check each part one by one on each part of the large layout.EssenceIn this way, you can complete the task faster.

The comparison of layout, the comparison of the schematic diagram and the design rules are the same as the inspection task. They are all modules. In essence, there is no data association between data comparison work, heavy memory requirements, and no data between sub -tasks. It is a high -combined task.Therefore, this stage is very suitable for using memory optimization resources on the cloud, and quickly complete the task through the method of violent pile resources.

The pearl on the crown of the simulation circuit-Rebate circuit

As the pearl on the crown of the simulation circuit, RF chip has always been considered as in chip designThe top of Huashan.

On the one hand, because the physical shape and peripheral media distribution of the radio frequency circuit will have a great impact on the transmission of radio frequency signals. Therefore, the design path is very difficult. In the early stage, a large number of simulation tests need to be performed. In order to ensure high frequency performance, the selection of materials is also very particular about the selection of materials.For example, gallium arsenide and nitride.

On the other hand, in order to ensure the balanced performance of various indicators of radio frequency chips, the performance requirements of many indicators need to challenge the circuit structure of the process limit or design innovation, which tests the accumulation of engineers' experience.

The radio frequency needs to use electromagnetic field simulation, and the three -dimensional space vector needs to be calculated.If the territory is cut into a piece of two -dimensional world, then the radio frequency is cut into a grain of three -dimensional space. Of course, it is more challenging, and the needs of computing power will also increase.

EncounterThe CPU cannot be satisfied, try to use GPU processing, but they are a good hand to process vector calculation.

At present, the three commonly used software of the electromagnetic field of RF circuit are:HFSS、EMX、ADS。

HFSS has more electromagnetic field simulation in intelligent manufacturing/automobile manufacturing scenarios, and also supports some chip design scenarios. EMX and ADS processing chip design scenarios are more extensive.Among them, the HFSS and 19 editions ADS support the GPU processing electromagnetic field simulation task, and after passing parallelization, the efficiency is very significant; EMX does not support the GPU mission as a universal plug -in in Cadence.

About the essence of calculating the order of magnitude

Single module, multi -module andThe TOP -level task is three types of calculation of order -level tasks. You can guess a single module task literally, and the amount of calculation is the least. As a result, the TOP -level task is the most calculated.

Single -module task refers to a single oneThe module task, for example, a certain elemental device on a single layer is a single module task. Calculate the smallest level and may continue to disassemble, or it may be the minimum inseparable task;

Multi -module tasks refer to the tasks that are combined with multiple single modules, such as modules combined with multiple components on the first layer. Calculate the medium level, and multiple modules can be split for multi -threaded processing;The TOP -level task, like its name, is a simulation of the scale of the entire chip design stage, gathers all the functional modules of the entire chip to make full functional verification.TOP -level simulation is a whole set of front imitation or rear imitation under the top view, and the computing power needs is the highest.

If it involves advanced crafts (Below 28nm), smaller space, more modules, more complicated PDK process libraries, the calculation amount is exponentially increased.And the independent examination of IR Drop after imitation after the advanced process chip is imitated, it is a necessary step for SIGNOFF.Most of the tools used in the industry are Redhawk, which is basically the same as the DRC/LVS algorithm process.

About simulationIC design, from the perspective of computing tasks at different design stages, we summarized three points:

1. The computing power demand of the three stages presents the trend of early & lt; mid -term & lt; later.Compared with the Big Valley, the highest computing power can be different. Using elastic cloud resources can efficiently and dynamically meet the peak requirements;

2. Multi -Corner, Monte Carlo Monte Carlo, and DRC and LVS tasks are very suitable for directly using multi -machine parallel to improve the task efficiency;

3. Based on a single module that cannot be demolished, although multi -machine distributed processing cannot be achieved, it can improve the task efficiency by the performance of the machine through large memory and high -frequency models.